Part 17. SIMD Instructions Harmful?

content by Xing Chen

Hereunder is a citation from the following post titled “SIMD Instructions Considered Harmful”: https://www.sigarch.org/simd-instructions-considered-harmful/

“In conclusion, as SIMD ISAs dictate the hardware, achieving greater data-level parallelism means changing the instruction set and the compiler. One can argue that SIMD violates the design principle of isolating architecture from implementation. In contrast, vector ISAs allow processor designers to choose the resources for data parallelism for their application without affecting the programmer or the compiler.”, posted by David Patterson (yes, the main contributor of RISC-V) and Andrew Waterman (the Chief Engineer at SiFive) on Sep 18, 2017.

“We think the high contrast in cost-energy-performance, complexity, and ease of programming between the vector approach of RV32V versus the ever expanding SIMD architectures of ARMv7, MIPS-32, and IA-32 is one of the most persuasive argument for RISC-V.”, cited from the same source.

https://www.sigarch.org/simd-instructions-considered-harmful

I would like to draw your attention, while reading this post, to the fact that it is comparing RV32V with ARMv7, MIPS-32, and IA-32; knowing very soon after the post, IA-32 production was stopped (around 2019), and nowadays the industry should have moved to 64 bits, at least for HPC/AI.

Another fact needs to be taken into account, while reading the post, is that SIMD was/is evolved/evolving; notably ARM side (I didn’t check AVX-512), Fujitsu A64FX as an example, nowadays the SIMD extension can also work with agnostic vector length, so part of the arguments of the post disappeared, but others still hold true, thus the post is still indicative and instructive, worth reading.

The Scalable Vector Extension (SVE) of Fujitsu A64FX is nicely explained, notably scalable vector length (VL) and VL agnostic (VLA) programming, by the following doc: https://indico.math.cnrs.fr/event/4705/attachments/2362/2901/ARM-SVE-Intro-190612.pdf

Happy reading!