The final set of my Fall 2021 graduate-level Computer Architecture course lectures are online with all videos, slides & course materials.

The course was livestreamed Sep-Dec 2021. 
We covered fundamentals & cutting-edge research in memory, interconnects, multiprocessors, GPUs, FPGAs, accelerators & hardware/software cooperation. 

Youtube playlist:
Course website:
Course schedule:

L1: Introduction & Basics
L2: Trends, Tradeoffs & Design Fundamentals
L3a: Memory Systems: Challenges & Opportunities
L3b: Course Info & Logistics
L3c & L4a: Memory Performance Attacks
L4b: Data Retention & Memory Refresh
L5 & L6a: RowHammer & Secure and Reliable Memory
L6b & L7: Processing using Memory
L8: Processing near Memory
L9a: Real PIM Systems: UPMEM Case Study
L9b: How to Evaluate Data Movement Bottlenecks
L10: Intelligent Genome Analysis
L11 & L12a: Low-Latency Memory
L12b: Memory Controllers
L13: Memory Controllers II: Performance & Service Quality
L14a: Memory Controllers III: Performance & QoS Wrap-Up
L14b: Emerging Memory Technologies
L15 & L16: Cutting-Edge Research in Computer Architecture
L15a: Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning
L15b: Google Neural Network Models for Edge Devices: Analyzing & Mitigating Machine Learning Inference Bottlenecks
L15c: CODIC: A Low-Cost Substrate for Enabling Custom In-DRAM Functionalities & Optimizations
L16a: Uncovering In-DRAM RowHammer Protection Mechanisms: A New Methodology, Custom RowHammer Patterns & Implications
L16b: A Deeper Look into RowHammer’s Sensitivities: Experimental Analysis of Real DRAM Chips & Implications on Future Attacks and Defenses
L16c: BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows
L16d: HARP: Practically & Effectively Identifying Uncorrectable Errors in Memory Chips That Use On-Die Error-Correcting Codes
L17a: Emerging Memory Technologies II
L17b & L18: Parallelism & Heterogeneity
L19a: Multiprocessors
L19b: Memory Ordering (Memory Consistency)
L20: Cache Coherence
L21: Interconnects
L22: On-Chip Networks
L23: SIMD Processors & GPUs
L24: Cutting-Edge Research in Comp Arch III
L24a: QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips
L24b: SynCron: Efficient Synchronization Support for Near-Data-Processing Architectures
L24c: SIMDRAM: An End-to-End Framework for Bit-Serial SIMD Computing in DRAM
L24d: NERO: A Near High-Bandwidth Memory Stencil Accelerator for Weather Prediction Modeling & FPGA-based Near-Memory Acceleration of Modern Data-Intensive Applications

1: Simulating & Exploring Cache Behavior 
2: Memory Hierarchy
3: Memory Request Scheduling 
4: Prefetching
5: Multicore & Cache Coherence 

SAFARI Research Group
ETH Zürich

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